A semiconductor integrated circuit includes an electro-static discharge (ESD) protection circuit for preventing destruction of an internal circuit due to ESD. An ESD is often generated from a human body during an assembly process of a semiconductor integrated circuit and a mounting process of a semiconductor circuit on a printed circuit board. Thus, it is necessary that a semiconductor integrated circuit includes a protection circuit that protects internal circuit elements from a high voltage surge due to ESD applied to an external terminal while powered off.
For example, Japanese Laid-open Patent Publication No. 2005-235947 and No. 2006-302971 discuss ESD protection circuits.
Japanese Laid-open Patent Publication No. 2005-235947 discusses protection of an internal circuit from a high voltage surge due to ESD by a transistor that temporarily turns on and increases a gate potential of a clamp transistor to turn on a bipolar transistor of a clamp transistor. Japanese Laid-open Patent Publication No. 2006-302971 discusses a power supply clamp circuit that is not turned on at an allowable level of power supply noise under normal operation.
As described above, various kinds of protection circuits that protect internal circuit elements from ESD have been proposed. However, ESD protection circuits are designed under assumption that all input and output terminals are at ground potential with power not supplied to an integrated circuit.
A latch-up test of Capacitance-Voltage (C-V) method for an in-car integrated circuit device is specified by the standard specifications that checks whether or not the integrated circuit device may protect an internal circuit element from a high-voltage surge of a power supply voltage that is generated with power on. In this latch-up test of C-V method, charges that generate a given high voltage surge to a power supply terminal and a signal terminal are applied with normal power supply being applied to an integrated circuit. It is assumed that a conventional ESD protection circuit operates under a condition that no power supply voltage is applied, and does not sufficiently protect an internal circuit from a high voltage surge which is applied to a power supply when the latch-up test of C-V method is executed.